What is this?
Overflow is an open-source hardware engineering project from the Dollbar organization at USTC that builds synthesizable RTL for an AI accelerator SoC (NPU plus KDLink interconnect), targeting a Kimi-K3-scale mixture-of-experts model as the reference workload.
Overflow is an open-source hardware engineering project from the Dollbar organization at USTC that builds synthesizable RTL for an AI accelerator SoC (NPU plus KDLink interconnect), targeting a Kimi-K3-scale mixture-of-experts model as the reference workload.Is this a working chip or just RTL source code?It's synthesizable RTL (hardware description code) plus a full verification stack, not silicon. External HBM, SerDes, host, and technology behavior are only represented by explicitly-labeled models.
It's synthesizable RTL (hardware description code) plus a full verification stack, not silicon. External HBM, SerDes, host, and technology behavior are only represented by explicitly-labeled models.How do I reproduce the release and run the verification gates?Clone the repo on a Linux x86-64 host with the required toolchain on PATH and run the Make-based regression; expect RELEASEREGRESSIONPASS and RELEASEGATEPASS as the output of the clean, licensed attestation.
Clone the repo on a Linux x86-64 host with the required toolchain on PATH and run the Make-based regression; expect RELEASEREGRESSIONPASS and RELEASEGATEPASS as the output of the clean, licensed attestation.What tools do I need installed before building it?Python 3.12, GNU Make, GCC, Verilator, Yosys, OpenSTA, and verilatorcoverage must be available on PATH; a 32 GiB RAM machine is recommended for the full RTL regression (single Pod lint alone used about 20 GiB).
Python 3.12, GNU Make, GCC, Verilator, Yosys, OpenSTA, and verilatorcoverage must be available on PATH; a 32 GiB RAM machine is recommended for the full RTL regression (single Pod lint alone used about 20 GiB).Does this release include a complete working chip or AI stack?No. The 1.0 release excludes model weights, private datasets, a full compiler/runtime/driver stack, an end-to-end Kimi-K3 product, analog PHY models, physical design, DFT, and silicon signoff; the headline performance numbers are simulation/architecture claims, not measured silicon.
No. The 1.0 release excludes model weights, private datasets, a full compiler/runtime/driver stack, an end-to-end Kimi-K3 product, analog PHY models, physical design, DFT, and silicon signoff; the headline performance numbers are simulation/architecture claims, not measured silicon.Who is this project for?It's aimed at hardware/RTL engineers and researchers working on AI accelerator SoC design, not end users running an AI model.
It's aimed at hardware/RTL engineers and researchers working on AI accelerator SoC design, not end users running an AI model.What is KDLink?KDLink is Overflow's chip-to-chip interconnect, covering endpoint, router, and collective RTL plus a vendor-neutral digital SerDes model used to link multiple NPUs together.
KDLink is Overflow's chip-to-chip interconnect, covering endpoint, router, and collective RTL plus a vendor-neutral digital SerDes model used to link multiple NPUs together.What workload does the architecture target?The baseline targets a Kimi-K3-style reference model with 2.8T total and 104B active parameters, with a forward-looking envelope of 5.6T total and 208B active parameters using MXFP4 weights and MXFP8/FP8/BF16 activations.
The baseline targets a Kimi-K3-style reference model with 2.8T total and 104B active parameters, with a forward-looking envelope of 5.6T total and 208B active parameters using MXFP4 weights and MXFP8/FP8/BF16 activations.How long does a full verification run take?On the validated 24-thread host, the KDLink RTL gate takes about 45 minutes and its instrumented coverage gate about 48 minutes; these are planning figures, not performance requirements.
On the validated 24-thread host, the KDLink RTL gate takes about 45 minutes and its instrumented coverage gate about 48 minutes; these are planning figures, not performance requirements.Are the 2 PFLOPS, 5 TB/s and 50 token/s numbers measured on real silicon?No, they are explicitly labeled as architecture or simulation claims (ANALYTICAL, FUNCTIONALSIM, RTLSIM, FORMAL, or GENERICSYNTH evidence levels), not measured silicon results.
No, they are explicitly labeled as architecture or simulation claims (ANALYTICAL, FUNCTIONALSIM, RTLSIM, FORMAL, or GENERICSYNTH evidence levels), not measured silicon results.What are similar projects?ai-infra-book, maths-cs-ai-compendium, apex-inference-chip, Hy-MT2, cs249r_book, DeepSeek-V3, professional-programming, openTPU
ai-infra-book, maths-cs-ai-compendium, apex-inference-chip, Hy-MT2, cs249r_book, DeepSeek-V3, professional-programming, openTPUWhich topics is it in?university, system-design, simulation, architecture, hardware, quantization, artificial-intelligence, distributed-systems, inference, testing, china, networking
university, system-design, simulation, architecture, hardware, quantization, artificial-intelligence, distributed-systems, inference, testing, china, networking